1. Field of the Invention
The present invention relates generally to content addressable memory access systems and methods, and more particularly to content addressable memory access systems and methods having self-timing and built-in margin test features.
2. Related Art
FIG. 1 illustrates a conventional content addressable memory (CAM) 102 for use in a computer system. The CAM 102 has a compare array 104, row drivers 108, and an access array 112.
The compare array 104 has N rows and M columns. Each column of every row contains a data bit and a comparator. Thus, every row in the compare array 104 has M data bits and M comparators.
The compare array 104 receives a compare input 106 having M bits. The compare input 106 is received by every row of the compare array 104. For every row in the compare array 104, the M comparators determine whether the M data bits match or mismatch the compare input 106.
Each row of the compare array 104 has a mismatch indication 122. Thus, there are N mismatch indications 122. A row's mismatch indication 122 is true if the compare input 106 does not match the row's M data bits. A row's mismatch indication 122 is false if the compare input 106 matches the row's M data bits.
The mismatch indications 122 are input to a row driver 108. The row driver 108 produces N row enables 118. The N row enables 118 correspond to the N mismatch indications 122. Specifically, a row enable 118i is asserted if its corresponding mismatch indication 122i is false.
Note that the compare array 104 and the row driver 108 have clock inputs 116 and 117, respectively. The clock inputs 116, 117 are used to determine when the compare array 104 and the row driver 108 receive the compare input 106 and mismatch indications 122, respectively. In other words, the clock inputs 116, 117 are used to determine when the compare input 106 and mismatch indications 122 are valid. As shown in FIG. 1, signals on the clock inputs 116, 117 are conventionally produced by a system clock 114.
The access array 112 has N rows wherein each row contains X bits of data. In other words, the access array 112 contains N data words wherein each data word contains X data bits. A data word in the access array 112 is accessed if its corresponding row enable 118 is asserted.
The CAM 102 operates as follows. All of the N mismatch lines 122 are precharged false (that is, high) during a low phase of the system clock 114. The compare array 104 receives the compare input 106. The compare input 106 either matches none or one or more of the rows in the compare array 104.
If the compare input 106 matches none of the rows in the compare array 104, then all of the mismatch indications 122 fall true. As a result, the row driver 108 does not assert any of the row enables 118. Thus, none of the data words in the access array 112 are accessed.
If the compare input 106 matches a row in the compare array 104, then the row's mismatch indication 122 remains false. As a result, the row driver 108 asserts the corresponding row enable 118 when the system clock 114 attached to the clock input 117 falls. Therefore, the data word in the access array 112 associated with the asserted row enable 118 is accessed.
The mismatch indications 122 must be valid when the row driver 108 uses the mismatch indications 122 to produce the row enables 118. This occurs when the system clock 114 attached to the clock input 117 falls. Otherwise, the row enables 118 will be invalid and a data word from the access array 112 may be incorrectly accessed.
As noted above, the clock inputs 116, 117 determine when the compare array 104 and the row driver 108 receive the compare input 106 and mismatch indications 122, respectively. More precisely, the compare array 104 receives the compare input 106 on a rising edge of the system clock 114 on the clock input 116. The row driver 108 receives the mismatch indications 122 on the subsequent falling edge of the system clock 114 on the clock input 117.
The amount of time between the rising edge and subsequent falling edge of the system clock 114 must be sufficient to allow the compare array 104 to generate valid mismatch indications 122. Otherwise, the row driver 108 will produce invalid row enables 118.
Ordinarily, the amount of time between the rising and subsequent falling edges from the system clock 114 is sufficiently large to allow the compare array 104 to generate valid mismatch indications 122. In fact, the amount of time necessary for the compare array 104 to generate valid mismatch indications 122 is significantly less than the amount of time between the rising and subsequent falling edges from the system clock 114. Thus, it is wasteful to use the system clock 114 to produce the second clock signal on the clock input 117. In other words, the system clock 114 does not provide an adequate measure of the amount of time it takes the compare array 104 to generate valid mismatch indications 122.
Therefore, the conventional CAM 102 is flawed because the exclusive use of the system clock 114 in its access mechanism lowers the rate at which the access array may be accessed.
Therefore, optimized systems and methods for accessing content addressable memories are required. Also, systems and methods for testing such optimized CAM access systems and methods are required.